
AT24C02A/04A
The AT24C04A uses the A2 and A1 inputs for hardwire addressing, and a total of four
4K devices may be addressed on a single bus system. The A0 pin is a no-connect.
WRITE PROTECT (WP): The AT24C02A/04A have a WP pin that provides hardware
data protection. The WP pin allows normal read/write operations when connected to
ground (GND). When the WP pin is connected to V CC , the write protection feature is
enabled and operates as shown.
Table 2. Write Protect
Part of the Array Protected
WP Pin Status
At V CC
24C02A
Upper Half (1K) Array
24C04A
Upper Half (2K) Array
At GND
Normal Read/Write Operations
Memory Organization
AT24C02A, 2K SERIAL EEPROM: The 2K is internally organized with 3 2 pages of 8
bytes each. Random word addressing requires an 8-bit data word address.
AT24C04A, 4K SERIAL EEPROM: The 4K is internally organized with 3 2 pages of 16
bytes each. Random word addressing requires a 9-bit data word address.
Table 3. Pin Capacitance (1)
Applicable over recommended operating range from T AI = 25 ° C, f = 1.0 MHz, V CC = +1.8V
Symbol
C I/O
C IN
Test Condition
Input/Output Capacitance (SDA)
Input Capacitance (A 0 , A 1 , A 2 , SCL)
Max
8
6
Units
pF
pF
Conditions
V I/O = 0V
V IN = 0V
Note:
1. This parameter is characterized and is not 100% tested.
3
0976Q–SEEPR–8/05